Development of Mobile Robot Based on I
2
C Bus System
201
component for hardware reconfiguration is implemented in the FPGA. Multiple sensors and
actuators with corresponding device drivers and signal processing modules are in the
sensor or actuator layer. Each control module consists of one or more input ports, one or
more output ports, and any number of other connections. The functionality of the module is
implemented to provide automatic integration of the control modules. The information
flow, communication and synchronization should be handled automatically by the
operating system.
4. The I
2
C bus system overview
The standard Inter-IC (Integrated Circuit) bus named I
2
C is shorthand providing a good
support for communication with various peripheral devices (Philips Semiconductor, 2000).
It is a simple, low-bandwidth, short-distance protocol. There is no need for chip select or
arbitration logic, making it cheap and simple to implement in hardware. Most I
2
C bus
devices operate at speeds up to 400 Kbps. The I
2
C bus system is easy to link multiple devices
together since it has a built-in addressing format. The I
2
C bus is a two wire serial bus as
shown in Fig. 15. The two I
2
C signals are serial data (SDA) and serial clock (SCL).
Fig. 15. The I
2
C bus has only two lines in total
It is possible to support serial transmission of eight-bit bytes with seven-bit bytes device
addresses plus control bits over the two wire serial bus. The device called the master starts a
transaction on the I
2
C bus. The master normally controls the clock signal. A device
controlled and addressed by the master is called a slave. The I
2
C bus protocol supports
multiple masters, but most system designs include only one. There may be one or more
slaves on the bus. Both masters and slaves can receive and transmit data bytes. The slave
device with compatible hardware on I
2
C bus is produced with a predefined device address,
which may be configurable at the board device.
Fig. 16. The I
2
C bus communication
The master must send the device address of the slave at the beginning of every transaction.
Each slave is responsible for monitoring the bus and responding only to its own address. As
shown in Fig. 16, the master begins to communicate by issuing the start condition. The
master continues by sending seven-bit slave device address with the most significant bit.
www.intechopen.com
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales